We have been using the Cadence tools for class work since the fall of 2001. The Virtuoso layout tool is used in ECEN 4303, ECEN 5263 and ECEN 6263, and the Ambit logic synthesizer and Verilog simulator are used in ECEN 5253 and ECEN 6253.
Accessing Cadence Software at OSU
See also CEAT Labs
Cadence On-Line Documentation
Inverter Layout Tutorial See also cadence online
documentation in file:/app1/cadence/doc/celltut/celltutTOC.html
Logic Gate Synthesis and Simulation
Graphics for Verilog Simulator Output
Auto Layout with MSU Standard Cells
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Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.
Last updated: Jan. 18, 2008 by Dr. Louis G. Johnson.